The present invention relates to high speed data interfaces, and more particularly to using a modified Data Mask (DM) pin as an error flag when de-skewing communications.
Graphics processing is an important feature of modern, high performance computer systems. Some graphical processing systems render high-resolution, real-time graphical images on display devices by using special high-performance computational circuitry that is incorporated into or that is otherwise mated with graphical processing units (GPUs).
In addition to GPUs and computational circuitry, graphical processing systems also require memory devices, usually high speed static random access memory (SRAM) or dynamic random access memory (DRAM). While SRAM and DRAM devices have been used with GPUs for many years, current demands for high resolution, high performance, real time graphics processing requires very fast memory devices. To that end, faster memory devices, such as double data rate random access memory, have been developed. A double data rate memory device clocks data into or out of memory on both the rising and falling edges of a clocking signal.
While double data rate memory devices are very useful, the sheer speed required to render high resolution digital images in real time can make the basic task of communicating with memory difficult. This is because high speed data accessing takes place over individual data lines that can differ. For example, individual data lines can have different lengths, distributed impedances, and end terminations. Those differences can cause individual bits of a data byte to arrive at a receiver at different times. Furthermore, individual receivers and drivers have transition speeds that can differ. For example, a GPU could send a data byte to a memory device with a first pattern, say 1111 0000, which, when clocked into a memory, could be recognized as 1011 0001 because the clock signal arrived before the data byte was ready to be clocked. This temporal problem is referred to as skew.
In some high speed interface circuits, for example double data rate memory, the actual clocking of data into and out of a memory device is performed using a strobe signal that is derived from a master clock. By selectively delaying the strobe signal relative to the data byte the strobe signal's edges can be shifted such that they occur after the data byte is ready. Reference U.S. provisional application No. 60/539,787 filed Jan. 27, 2004, incorporated by reference, which describes how to automatically shift strobe timing such that the strobe edges occur at times that avoid skew.
While the teachings of U.S. provisional application No. 60/539,787 filed Jan. 27, 2004 are beneficial, implementing those teachings are subject to practical constraints. For example, when adjusting strobe timing relative to data packets during WRITE de-skew training, some method of informing the GPU about the results of strobe timing is required. A straightforward way to do that would be to add a new “result” pin to the memory device and another to the GPU. Unfortunately, SRAM and DRAM memory devices, particularly, their input/output (I/O) pin configurations, are relatively standardized. While adding internal circuitry to a GPU and to a memory device to implement de-skew training is relatively straight forward, adding a new I/O pin is contrary to accepted standards.
Therefore, a method and apparatus that enables a memory device to inform a graphics processing system about the results of de-skew training during WRITE operations would be beneficial. Also beneficial would be a method and apparatus that enables a memory device to signal a graphics processing system about strobe timing relative to data packets during WRITE operations using existing memory pin-outs.